A 0.67-mm/sup 2/ 45-/spl mu/W DSP VLSI implementation of an adaptive directional microphone for hearing aids

A promising algorithm implementing an adaptive directional microphone for hearing aids is investigated. The full complexity of the algorithm is revised to keep within the tight consumption requirements imposed by hearing aid batteries while not compromising the performance. Fixed-point quantization and simplified arithmetic operations are discussed on the basis of SNR (signal to noise ratio) degradation. A compact VLSI design, exploiting different low-power techniques, is implemented targeting a 0.25/spl mu/m CMOS process. The estimated power consumption (45/spl mu/W at 1.25V) of the final layout (0.67mm/sup 2/), together with the good performance of the algorithm, indicate this small block is worth being included in modern hearing aid ASICs.