Evaluation strategies for coarse grained reconfigurable architectures

The granularity of a reconfigurable architecture has a big impact on important properties such as output data rate, area and energy consumption. Fine-grained architectures such as SRAM-based FPGAs provide good flexibility and speed, but they suffer from poor area efficiency, since the programmable interconnection network produces most of the die area. In contrast to FPGAs, coarse-grained architectures incorporate more complex processing cells that may include ALUs, multipliers and embedded memory. These structures provide much better area efficiency, while still being flexible enough for the application domain to which they have been designed. In this paper we present an approach for quantifying the impact of the granularity of a reconfigurable architecture on speed and area consumption. Our approach is based on a physical model, which enables us to compare the results to other implementation forms such as DSPs and non-reconfigurable standard cell designs.