CDF(2,2) wavelet lossy image compression on primitive FPGA (XC9572)

This paper presents a hardware implementation of CDF(2,2) wavelet image compressor. The design demonstrates that high quality circuit implementation is possible through the use of suitable data organization (partitioned approach) and algorithm-to-architecture mappings (parallelism or pipelining). The main goal is to reach a higher performance and throughput with a single primitive FPGA device namely, Xilinx's XC9572. Details of the encoder design have been discussed and the results are presented.