TCAM enabled on-chip logic minimization

This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory efficient implementation suitable for emerging on-chip minimization applications. The paper presents a detailed design of the on-chip minimizer and shows that it requires very little hardware resources to achieve acceptable quality of minimization. An incremental insertion and bulk deletion is achieved in 0.25 /spl mu/s and 3.8 ms respectively and a compaction of 100000 entries in 25 ms using just 300 TCAM entries.