Limits for switching power consumption in encoded interconnects

Power consumption emerged as a key performance and cost limiting factor in CMOS integrated circuit design. As technology shrinks, the required interconnection structures increasingly affect the overall power consumption, performance and area requirements. Therefore, signal encoding has been proposed as an efficient way to reduce the switching power consumption in buses. The goal of this work is to determine the realizable lower bound of encoding-based schemes that reduce switching power consumption. These limits can be employed at higher levels of abstraction to give information about the maximum achievable encoding-based power savings without any knowledge on the optimal encoding scheme. Moreover, the algorithm developed in this work can also be used to construct those optimal encoding schemes in a more efficient way than previously proposed techniques.