Technological and architectural power optimizations for advance microprocessors

Reliability, thermal management, packaging cost, and suitability for mobile devices, are making power consumption a main concern for high-end microprocessors. In order to tackle this problem, power efficient design techniques addressing all the abstraction levels are required. To satisfy the demands of increasing functionality and higher processing power, the design of high-end microprocessor must face two main challenges. On the one hand, it must be implemented in highly compact nanoscaled technologies. On the other hand, it must handle the increased design complexity, especially from a power-efficient perspective; it is, with the use of power management techniques. This paper describes some of the low power design strategies of the PowerPC/sup /spl trade//970 microprocessor in the aforementioned two directions: technology scaling and power management. The goal is to show that power efficiency requires a global strategy addressing simultaneously different levels of abstractions.