Realization of N-D signal processing tasks in high-speed applications

The present paper describes initial aspects of a framework for realization of n-D signal processing tasks under rigorous budgetary demands, as usually found in industrial applications. Besides design on the basis of adequate guidelines, development of algorithms with respect to a dedicated hardware platform is an important means of optimization. An exemplary realization of a hand detection device is presented, which incorporates several efficient algorithms that are limited in accuracy but in combination lead to a robust hand detection algorithm. These basic processing blocks are mainly based on FPGA realizations of well known FIR filter structures in combination with convolution-like operations based on Boolean logic instead of complex arithmetic. One example for this class of algorithms is binary morphology, which can be realized in low-cost FPGAs for high data throughput of several Gpixel per second and with large operator masks, e.g. with 25/spl times/25 pixels in size.