An implementation of turbo decoder for high speed wireless packet transmission system

This paper proposes an efficient implementation of turbo decoder used in joint detection and decoding receiver. The work is based on high speed wireless packet transmission system. The turbo decoder get soft information of coded bits from the detector and feedback it the updated soft information. And the joint detection and decoding adopts extrinsic information reserved approach. Turbo decoding uses log-MAP algorithm. To maximize the reusability of hardware resource, we adopt the single-RSC-decoder structure and the calculations of the path metrics share one recursion unit. Sliding-window approach is used to further reduce the memory usage for internal metrics. We calculate the dynamic range of all internal metrics in this paper, and the module normalization method has been used to avoid data overflowing. The final turbo decoder consumes 1,057 slices and 25 block RAMs of the FPGA device and achieve a throughput of more than 15 Mbps with 3 iterations. With input soft information of 5 bits (32 levels), the implemented turbo decoder results in about 0.2 dB loss of E/sub b//N/sub o/ from the optimal floating point turbo decoder.