A new fast algorithm for 8/spl times/8 2-D DCT and its VLSI implementation

Due to the importance of the discrete cosine transform (DCT) in the field of transform coding of images, various algorithms and architectures for real-time 2-D DCT processor designs have been proposed. In this paper we present a new fast algorithm for 8/spl times/8 2-D DCT based on partial sum and its corresponding hardware architecture for VLSI realization. The algorithm costs fewest multipliers in theory and the system is a serial-in serial-out system. Theoretical proof and simulation results on FPGA devices show the efficiency of the algorithm. The kernel architecture corresponding to the algorithm is regular with lower complexity and performs high throughput.