Design of transceiver circuits for NRZ signaling in inductive inter-chip wireless superconnect

Recently, a 3-dimensional integrated circuits (3D-ICs) are appeared for high density packaging. High speed interconnection is expected in 3D-ICs. A wireless bus for stacked chips is presented in this paper. The interface utilizes inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero (NRZ) signaling were developed to reduce the power and achieve high data rate. Receiver circuit's timing margin and sensitivity is discussed. Test chip was fabricated and timing margin was measured. The result agrees very well with simulation. Then crosstalk reduction techniques for channel array are proposed and its efficiency is demonstrated by test chip. The chip has 3/spl times/65 channel array, each channel's performance is 1 Gbps, and maximum data rate of 195 Gbps are achieved by using proposed cross talk reduction techniques.