A 10-bit 2.5 mW 0.27 mm/sup 2/ CMOS DAC with spike-free switching

A low-power digital-to-analog converter for portable electronics is introduced A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18 /spl mu/m 1P6M CMOS standard technology, and its core area is 0.27 mm/sup 2/. The simulation results show the DNL/INL is /spl plusmn/0.14/0.14 at a conversion rate of 10 MHz, and consume 2.5 mW of power from a 1.8 V supply voltage.