Impact of on-die decoupling on the core and IO supplies of high performance microprocessors

In this paper, we present an empirical validation of the power supply decoupling with particular emphasis on on-die capacitance. We investigate the effect of the decoupling on both the core and IO performance. The validation approach consists of building several silicon wafers of high performance processors with various amounts of decoupling. Extensive measurements are then done at the silicon, package, and system levels. Finally we offer some theoretical insights to explain the unexpected behavior.