A nor-type MLC ROM with novel sensing scheme for embedded applications

3 bits per cell nor-type MLC ROM, multi layer cell read only memory macro of 4M bits density is presented. The MLC ROM is designed by a 0.18 /spl mu/m CMOS logic process. The ROM cell of 0.80/spl mu/m /spl times/ 0.90/spl mu/m with 0.05/spl mu/m per step of the channel width and channel length increase is determined to obtain 16 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 10 ns.