A novel CMOS compatible embedded nonvolatile memory with zero process adder

We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteristics. A strategy for optimizing programming efficiency is identified with the addition of one extra mask to introduce drain optimization implants.