Assertion based verification: have I written enough properties?

In recent times, assertion-based verification (ABV) has become an essential component of the pre-silicon design validation flow. However, the use of ABV to validate descriptions of systems during simulation lacks a proper coverage metric. We consider the task of determining the coverage of a set of assertions against a high-level stuck-at fault model. Such a coverage analysis can aid the verification engineer to add more assertions to enhance his property suite.