Extremely-scaled double-gate CMOS with non-self-aligned back gate

This paper presents the possibly viable concept of extremely-scaled but non-self-aligned planar DG CMOS technology that, irrespective of moderate back-gate underlap, can still yield high performance and low leakage with good control of short-channel effects (SCEs). The pragmatic design exploits the inherent beneficial features of both asymmetrical and symmetrical DG FETs as presented in H.S.P Wong et al. (1994), H. Hanafi et al. (2003), E. J. Nowak et al. (2004) and K. Kim and J. G. Fossum (2001), as well as the flexibility in their structural design. Off-state current (l/sub off/) reduction by reverse back-gate bias in DG device is studied and compared with the reverse body bias based in A. Keshavarzi et al. (2001) in bulk-Si counterpart.