A novel process-induced strained silicon (PSS) CMOS technology for high-performance applications

We report an optimized process-induced strained silicon (PSS) technology for 90nm CMOS generation and beyond. Through the superposition of various PSS techniques, up to 20% performance enhancement is achieved for both N- and PMOS at channel length down to 45nm. The PSS technology exhibits excellent gate oxide breakdown characteristics, isolation characteristics and reliability. A novel spacer-PSS technology is also proposed for the first time and /spl sim/7% enhancement in ring oscillator speed is observed.