A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications

A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-V/sub dd/ and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum V/sub dd/ of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.