Clock distribution on a dual-core, multi-threaded Itanium/sup /spl reg//-family processor

Clock distribution on the 90 nm Itanium/spl reg/ processor, code-named Montecito, is detailed. A region-based active de-skew system reduces the PVT sources of skew across the entire die during normal operation. Clock vernier devices inserted at each local clock buffer allow up to a 10% clock-cycle adjustment via firmware or scan. The system supports a constantly varying frequency and consumes <25 W from the PLL to latch while providing <10 ps of skew across PVT.