A 350MHz low-OSR /spl Delta//spl Sigma/ current-steering DAC with active termination in 0.13 /spl mu/m CMOS

A time-interleaved architecture overcomes the dynamic performance limitations of standard DWA switching. Clocked at 350MHz, the DAC with active output buffer achieves a linearity of 76dB for a signal swing of 1.536V and an effective resolution of 11.9b in a bandwidth of 29.16MHz. It is fabricated in a standard 0.13 /spl mu/m CMOS process and consumes 62mW from a 1.5V supply.