Significant improvement in reliability of HfSiON gate insulator

Instability during positive bias temperature (PBT) and channel hot carrier (CHC) stresses in an nFET is studied for a HfSiON gate insulator with an interface layer formed by several methods. The threshold voltage shift (/spl Delta/V/sub th/) during PBT stress shows strong dependence on the gate dielectric structure. Significant improvement is observed for HfSiON/SiON and post-deposition-annealed HfSiON being almost equivalent to the SiON reference, while HfSiON/chemical oxide shows large /spl Delta/V/sub th/. The result is discussed in terms of electron trapping efficiency in the HfSiON layer. The CHC is also shown to have similar dependence on the gate dielectric structure.