ESD protection window targeting using LDMOS-SCR devices with PWELL-NWELL super-junction

A variety of analog applications require an extension of the low-voltage process capabilities towards 12-20 volts or higher for a limited number of pins. The most cost effective way to achieve this is to extend low-voltage sub-micron CMOS processes by the implementation of extended voltage lateral BJT, self-aligned lateral DMOS (LDMOS) and non-self aligned devices with an extended drain, either using existing CMOS process regions (Dolny, G.M. et al., 1986) or by adding a few extra regions. The ESD protection of these high-voltage devices in the low-voltage process presents a new challenge. The most robust way to protect the extended voltage LDMOS devices is by the implementation of a silicon controlled rectifier LDMOS-SCR structure (Concannon, A. et al., 2004). The paper focuses on a device level solution for the control of both the breakdown voltage and the triggering characteristics of the extended voltage ESD devices. This was achieved by the use of super-junctions (multi-RESURF) (Deboy, G. et al., 1998; Xu, S. et al., 2000) and diluted-junctions (Vashchenko, V.A. et al., 2004) widely used for discrete power devices.