Random charge effects for PMOS NBTI in ultra-small gate area devices

PMOS transistor degradation due to negative bias temperature instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.