Promissing new fabrication process developed for stacked LSI's

A stacked CMOS LSI fabrication process has been developed for the purpose of realizing a short fabrication turn-around time, high fabrication yield and high integration density. This process consists of, in addition to the conventional LSI process, fabrication of vertical interconnections, surface planarization and thermal compression to obtain electrical interconnections between 2 layers. A 2-layer, bulk/CMOS ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been made using this new fabrication process. It has 31 bulk/CMOS inverter stages, each of which contains a single Au vertical interconnection with area of 10 × 10 µm
²
. A typical propagation delay time per stage for this device is measured to be 1.86 nsec at a supply voltage of 5 V.