Suppressing latchup in insulated gate transistors

Two-dimensional computer modeling of insulated gate transistor (IGT) structures has been used to demonstrate the suppression of latchup in the parasitic thyristor by increasing the p-base conductivity using a deep p+ diffusion in the device cells. Experimental verification of these modeling results has been performed with thyristor latching current density of over 1000 A per cm
²
achieved in 600-V devices at room temperature.