High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage

The design of an ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array applications is presented. The circuit features an AC-coupled dynamic current source to improve the power-delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8- mu m double-poly, self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.62* (1.90*) improvement in the speed (load driving capability) of a loaded gate compared with the conventional ECL circuit.<
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