Comparison of various source-gate geometries for power MOSFET's

A simplified model is used to compare the influence of layout geometry on the parasitic drain resistance of a vertical DMOSFET. For each case, optimum dimensions are determined. For every geometry considered at least one-half of the total area is available for current conduction. The hexagon has been favored by some workers but slightly better results can be achieved with rectangles or with circles on hexagonal centers.