A new super high speed ECL compatible I2L technology

A new technology for realizing high performance I
²
L and high speed ECL circuits on a same chip is described. The key to such a technology is graft base structure having respectively optimized impurity profiles for I
²
L gates and linear transistors. All of base regions (I
²
L; P
⁺
, P
^--
, a linear transistor; P
⁺⁺
, P
^-
) are formed in different doping steps, followed by only one n
⁺
diffusion for I
²
L collector and the linear transistor's emitter. I
²
L P
^--
intrinsic base region formed by high energy ion implantation has a smaller Gummel number and a deeper junction depth than in the linear transistor. I
²
L P
⁺
extrinsic base region is deeper in junction depth than linear P
⁺⁺
base region. A high speed I
²
L gate with upward current gain of 30 and 7 ns minimum delay could be compatible with a linear transistor having downward current gain of 80, BV
CEO
of 18 V and 4 GHz maximum cut off frequency. Futhermore, an ECL divider has successfully operated at frequencies up to 1.4 GHz.