Subnanosecond ED MOS IC using new technology

A new integrated MOS structure which is featured with high speed, low applied voltage, low power and high packing density has been developed using Elevated Electrode IC technology. The arsenic doped polysilicon with an overhanging edge is used as a part of gate electrode. In the metal evaporation process, the shadowed area under the edge separates the source, drain and gat electrodes without fine photolithography and etching processes.