FET circuit destruction caused by electrostatic discharge

Under certain environmental conditions, electrostatic discharges can cause catastrophic failure in both bipolar and FET integrated circuits [1]. Some devices (MOSFET's) are particularly susceptible to damage because of the relatively low destructive breakdown voltage (50 to 100 V) of their thin oxides. One source of concern is discharges from the human body during handling. This problem can be minimized by taking various approaches, such as 1) manufacturing the device so it has a high oxide breakdown voltage, 2) adding a protective device to the input, 3) developing special handling procedures to prevent high voltages from being applied to the devices accidentally. The objectives of this paper are to present a technique to test the effectiveness of FET protective devices using a simulated human static discharge and also to present a mathematical model that can predict a catastrophic failure as a function of voltage developed across the FET device and the energy dissipated. Both theoretical and experimental data are presented.