Bipolar integrated circuits formed in P-type epitaxial layers

A new integrated circuit fabrication scheme, using transistors with p-type epitaxially grown base layers was proposed by the authors at the 1968 ISSCC. Transistor-transistor logic gates having a packing density of
1.1 \times 10^{5}
gates/in
²
have been fabricated using this scheme. The gates have a power × delay of 8 picojoules and a delay of 20 nsec using a 1.5 volt power supply. The output transistors have a peak f
t
of 2-3.4 GHz.