Efficiency analysis of a high frequency buck converter for on-chip integration with a dual -VDDmicroprocessor

An analysis of the power characteristics of a buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A parasitic model of the buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2 volts to 0.9 volts while supplying 9.5 amperes average current assuming an 80 nm CMOS technology. The area occupied by the buck converter is 12.6 mm
²
. An analytic estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high efficiency buck converter on the same die with a dual-V
DD
microprocessor is shown to be feasible.