A low power symmetrically pulsed dual edge-triggered flip-flop

A dual-edge triggered flip-flop suitable for low power applications is presented. HSPICE simulations conducted in 0.11u CMOS technology using 1.2V power supply voltage show that the proposed design is comparable in energy-delay product to high-performance single-edge triggered flip-flops while maintaining lower clock power. The Energy-Delay Product improvement of 14% and 50% smaller clock load compared to previously best published dual edge-triggered storage elements are demonstrated.