A novel sub -1 V high speed circuit design technique in partially depleted SOI-CMOS technology with ultra low-leakage power

As supply voltage is scaled to below 1 V, leakage power becomes significant in CMOS ICs. This paper proposes a new circuit style in PD-SOI technology to reduce standby power in the sub-1 V regime by over three orders of magnitude while maintaining circuit speed and with minimal overhead. It makes use of dual-V
TH
transistors to suppress leakage current in standby mode but uses a simple positive body biasing technique in active mode to reduce VTH and boost circuit speed. This scheme can be applied to both static and dynamic logic circuits in a variety of ways and is illustrated in this paper. Simulation results obtained using process parameters from an IBM 0.13 µm PD-SOI technology show considerable improvement over previously proposed methods as supply voltage is scaled to 0.5 V.