A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock

This paper describes a 4-Gb/s clock and data recovery circuit exploiting a four-phase 1/8-rate clock technique for low-power and high-speed operation. The voltage-controlled oscillator with an active inductor load provides the 50% duty-cycle correction operating at 1/8-rate clock. The four-phase detector performing 1:4 DEMUX accomplishes a linear frequency and phase detection with no systematic phase offset. Test chip was fabricated by a 0.25-µm digital CMOS technology. The peak-to-peak jitter of the recovered clock is 47ps for a PRBS of length 2
³¹
-1. The power dissipation is 70mW with a 2.5-V supply.