250 MHz CMOS rail-to-rail IO OpAmp: Structural design approach

A structural methodology is shown on the example of design of the industry fastest CMOS OpAmp implemented on the 0.6 um single n-well process. This OpAmp has rail-to-rail input/output, 250 MHz unity gain bandwidth, 350 V/us slew rate, >100 dB open-loop gain with 150 Ohm load, 6 nV/√Hz noise and consumes 5 mA from 2.5-5.5 V supply. Considered are the constant-g
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rail-to-rail input stage, DC gain boost, slew rate boost, folded cascode implementation, overload recovery improvement.