A 5.3GHz programmable divider for HiPerLAN in 0.25 µm CMOS

A 5.3 GHz low voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D flip-flop (DFF). An improved glitch-free phase switching technique through the use of a retimer circuit is introduced. A high speed low voltage DFF circuit is given. The programmable divider fabricated in 0.25µm technology occupies 0.09mm
²
and consumes 24mA at 1.8V and 37mA at 2.2V. 5.5GHz operation with 300mV
pk
single ended input is achieved with a 2.2V supply. The residual phase noise at the output is -130 dBc/Hz at an offset of 1kHz from the carrier.