A study of CMOS 2.0V low power pager receiver for the FLEXTMpaging system

The 0.4µm CMOS receiver IC for the FLEX^TMpaging system is designed and fabricated to integrate analog and digital building blocks onto a single chip in the near future. To study the influences of the digital switching noise into analog building blocks, a digital noise source block is implemented with the receiver IC. The receiver IC contains a 2nd mixer, a limiting amplifier, a detector, base-band amplifiers and a bit rate filter, and satisfies the specification of the FLEX^TMpaging systems. The receiver IC consumes 2.8mW(1.4mA × 2.0V) in the receiving mode.