A full-custom self-timed DSP processor implementation

Asynchronous self-timed control and DCVSL logic have been used in the construction of a complete VLSI processor, targeted for DSP algorithms. The 16-bit architecture includes both data and program memory, and uses a data-stationary control structure. The experimental VLSI circuit includes 143 000 transistors and has been fabricated using 0.8µm CMOS.