Selective-capacitance constant-charge-injection programming scheme for high-speed multilevel AG-AND flash memories

The market for flash memories has emphasized bit-cost reduction and high programming throughput because of demanding applications such as high quality digital still cameras and portable video recorders. One of the solutions to achieve low cost-per-bit is the multilevel cell (MLC) technique. However, the MLC technique requires precise control of the memory cell's threshold voltage (V/sub th/). A V/sub th/ distribution of a multilevel (four-level) memory cell is presented. When the memory cell is programmed to a higher level, program/verify operations must be performed to yield a narrow V/sub th/ distribution. Therefore, particular attention is paid to suppress the deviations of the programming characteristics in order to reduce the number of those operations and enhance programming throughput. To suppress the deviations, constant-charge-injection programming (CCIP) has been developed in assist-gate (AG)-AND flash memories. At the 90-nm node, however, this technique is insufficient. In this paper, we present a new highspeed multilevel programming method called selective-capacitance CCIP scheme that has achieved a programming throughput of 10 MB/s in 4-Gbit multilevel AG-AND flash memory.