A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

A 20GHz phase-locked loop with 4.9ps/sub pp//0.65ps/sub rms/ jitter and -101.2dBc/Hz phase noise at 1MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled-microstrip resonator. Static frequency dividers made of pulsed latches operate faster than a flip-flop based divider and achieve near 2:1 frequency range. The PLL fabricated in 0.13/spl mu/m CMOS operates from 17.6GHz to 19.4GHz and dissipates 480mW.