Flash ETOX/spl trade/ virtual ground architecture: a future scaling direction

A 65nm generation virtual ground (VG) ETOX/spl trade/ flash memory process capable of MLC operation and relying on a conventional channel hot electron program and F-N tunneling channel erase has been demonstrated. Several key process elements were successfully integrated to achieve functional test structures with 0.0315 /spl mu/m/sup 2/ cell size. The significant area scaling benefit was achieved in large part by replacing the drain contacts and metal interconnect in the array with a buried bitline diffusion implant. In addition to achieving the significant reduction in cell size, such an approach offers several important technological advantages compared to the conventional approach used by its predecessor technology and provides a promising path for continued future scaling of flash memories.