Nonvolatile MOSFET memory based on high density WN nanocrystal layer fabricated by novel PNL (pulsed nucleation layer) method

We describe a novel technique of fabricating WN nanocrystal memory device. Pulsed nucleation layer (PNL) method is firstly introduced for the formation of uniformly distributed high density (/spl sim/ 1.6 /spl times/ 1012 /cm/sup 2/) nanocrystals with the size of 3 /spl sim/ 5 nm. The WN nanocrystal memory exhibits very large threshold voltage shifts over 3.5 V and good retention and endurance characteristics. Further improvement of memory performances using stacked tunnel barrier and double layer storage node structures was also presented.