Advantages of gate work-function engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low-power CMOS

The impact of gate work-function (WF) engineering on low-power devices is investigated by incorporating sub-monolayer Hf at SiON/poly-Si interface. An increase of threshold voltage (V/sub T/) by WF control allows the use of lower substrate impurity concentrations. This leads to significant increase of carrier mobility and thus I/sub ON/. Moreover, the gate leakage current is reduced by WF control due to the decrease of oxide field or the increase of barrier height. We successfully demonstrate improvement of 16 % (nFET) and 5 % (pFET) in I/sub ON/ for 65-nm LOP devices when V/sub dd/ = 0.9 V.