The performance improvement of a photo card reader by the use of a high-integration chip solution with double FIFO buffers

The insufficient bandwidth of SDRAM access has created a bottleneck in the performance of displaying and processing when used in previous design of the photo card reader. In this paper, we propose three ways to overcome this drawback. First, we double the clock rate of the SDRAM operation to increase the amount of the memory bandwidth. Second, we use a dual port design of the SDRAM with a double buffer for the strip module to increase the usage efficiency of the bandwidth. Third, we also use a double buffer for the mem/spl I.bar/ctrl module to increase the usage efficiency of the bandwidth. Using the extra gate counts of double FIFO buffers results in an increase of 3.3% from the previous system. Our new design has an improvement in the processing speed of about 4.4 times for displaying photos.