On-chip accumulated jitter measurement for phase-locked loops

A time-to-digital converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL. Including the most positive jitter and the most negative jitter, the worst case jitters can be calculated through the proposed approach. In a case-study, by applying the proposed TDC circuit with 4-bit flash ADC and the accumulated period N=8, the frequency range of the measured signal, resolution and linearity error are 0.7-1.4GHZ, 44ps and 1.25%, respectively. Using a 0.25um 1P6IM CMOS process, the HSPICE simulation result shows that the maximum measurement error is 1 LSB after calibration.