A system-level approach to hardware reconfigurable systems

There is trend towards networked and distributed hardware reconfigurable systems, complicating the design process at the system-level. This paper provides a solution to the problem of design space exploration for such embedded systems of the next generation. We show the problems occurring while exploring the design space at the system-level, leading to new properties for valid implementations. The novelty of this approach lies in the support of explicit communication modeling and time-multiplexed architecture modeling in a single model. The proposed design space exploration is based on evolutionary algorithms and a new slack-based list scheduler.