Design of an efficient memory-based DVB-T channel decoder

A highly efficient implementation of a channel decoder for the terrestrial digital video broadcast (DVB-T) standard is presented. The DVB-T channel decoder is mainly composed of four major modules which all require significant amounts of intermediate data storage. The main contribution of the paper is to propose a suitable architectural solution for each individual module to achieve efficient realization of the data storage mostly by single-port memory blocks. Our implementation result shows that the core area of the entire DVB-T channel decoder IP (intellectual property) can be realized in less than 8 mm/sup 2/ in 0.35-/spl mu/m TSMC technology.