A macro-model for the efficient simulation of an ADC-based RNG

We present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35 /spl mu/m CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests that assure the quality of the output stream.