An 8b 240 MS/s 1.36 mm/sup 2/ 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs

This work describes a two-step pipelined 8 bit 240 MS/s 0.18 /spl mu/m CMOS ADC as one of the embedded cells for high-performance displays requiring low-noise on-chip references and dual-mode inputs with the specifications of limited pins, low power, and small size at high speed. The prototype ADC shows a measured DNL and INL within 0.49 LSB and 0.69 LSB, a SNDR exceeding 38 dB, and an SFDR exceeding 50 dB for inputs up to the Nyquist frequency at 240 MS/s. The ADC consumes 104 mW and the active die area is 1.36 mm/sup 2/.